Method of fabricating a multi-die semiconductor package assembly

ABSTRACT

An apparatus and method for increasing integrated circuit density comprising an upper die and a lower die, the latter preferably a flip chip, which are connected to a conductor-carrying substrate or a leadframe. The upper die is attached back-to-back to the lower die with a layer of adhesive applied over the back side of the lower die. Bond wires or TAB leads are attached between bond pads on the upper die and corresponding conductive trace or lead ends on the substrate. The upper die may be smaller than the lower die such that a small discrete component such as a resistor, capacitor, or the like can be attached to the adhesive not covered by the upper die. Bond wires can be attached between the upper die and the component, as well as between the component and the substrate. One or more additional die may be stacked on the upper die and electrically connected to the substrate. Furthermore, multiple lower dice can be arranged on the substrate to support upper dice bridged between the lower dice.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 08/602,503,filed Feb. 20, 1996, now U.S. Pat. No. 7,166,495, which issues Jan. 23,2007. The disclosures of each of the previously referenced U.S. patentapplications and patents (if applicable) referenced is herebyincorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus and a method forincreasing semiconductor device density. In particular, the presentinvention relates to a vertical multi-chip device using combinedflip-chip and wire bond assembly techniques to achieve densely packagedsemiconductor devices, and a method for producing such devices.

2. State of the Art

Definitions: The following terms and acronyms will be used throughoutthe application and are defined as follows:

BGA—Ball Grid Array: An array of minute solder balls disposed on anattachment surface of a semiconductor die wherein the solder balls arerefluxed for simultaneous attachment and electrical communication of thesemiconductor die to a printed circuit board.

COB—Chip On Board: The techniques used to attach semiconductor dice to aprinted circuit board, including flip-chip attachment, wire bonding, andtape automated bonding (“TAB”).

Flip Chip: A chip or die that has a pattern or array of terminationsspaced around the active surface of the die for face down mounting ofthe die to a substrate.

Flip-Chip Attachment: A method of attaching a semiconductor die to asubstrate in which the die is inverted so that the connecting conductorpads on the face of the device are set on mirror-image pads on thesubstrate (such as a printed circuit board), and bonded by solder refluxor a conductive polymer curing.

Glob Top: A glob of encapsulant material (usually epoxy or silicone or acombination thereof) surrounding a semiconductor die in a COB assembly.

PGA—Pin Grid Array: An array of small pins extending substantiallyperpendicularly from the major plane of a semiconductor die, wherein thepins conform to a specific arrangement on a printed circuit board orother substrate for attachment thereto.

SLICC—Slightly Larger than Integrated Circuit Carrier: An array ofminute solder balls disposed on an attachment surface of a semiconductordie similar to a BGA, but having a smaller solder ball pitch anddiameter than a BGA.

State-of-the-art COB technology generally consists of threesemiconductor die to printed circuit board conductive attachmenttechniques: flip-chip attachment, wire bonding, and TAB.

Flip-chip attachment consists of attaching a semiconductor die,generally having a BGA, an SLICC or a PGA, to a printed circuit board.With the BGA or SLICC, the solder or other conductive ball arrangementon the semiconductor die must be a mirror-image of the connecting bondpads on the printed circuit board such that precise connection is made.The semiconductor die is bonded to the printed circuit board byrefluxing the solder balls. With the PGA, the pin arrangement of thesemiconductor die must be a mirror-image of the pin recesses on theprinted circuit board. After insertion, the semiconductor die isgenerally bonded by soldering the pins into place. An under-fillencapsulant is generally disposed between the semiconductor die and theprinted circuit board for environmental protection and to enhance theattachment of the die to the board. A variation of the pin-in-recess PGAis a J-lead PGA, wherein the loops of the Js are soldered to pads on thesurface of the circuit board. Nonetheless, the lead and pad locationsmust coincide, as with the other referenced flip-chip techniques.

Wire bonding and TAB attachment generally begins with attaching asemiconductor die to the surface of a printed circuit board with anappropriate adhesive, such as an epoxy. In wire bonding, a plurality ofbond wires is attached, one at a time, to each bond pad on thesemiconductor die and extend to a corresponding lead or trace end on theprinted circuit board. The bond wires are generally attached through oneof three industry-standard wire bonding techniques: ultrasonicbonding—using a combination of pressure and ultrasonic vibration burststo form a metallurgical cold weld; thermocompression bonding—using acombination of pressure and elevated temperature to form a weld; andthermosonic bonding—using a combination of pressure, elevatedtemperature, and ultrasonic vibration bursts. The die may be orientedeither face up or face down (with its active surface and bond padseither up or down with respect to the circuit board) for wire bonding,although face up orientation is more common. With TAB, ends of metalleads carried on an insulating tape such as a polyimide are respectivelyattached to the bond pads on the semiconductor die and to the lead ortrace ends on the printed circuit board. An encapsulant is generallyused to cover the bond wires and metal tape leads to preventcontamination.

Higher performance, lower cost, increased miniaturization of components,and greater packaging density of integrated circuits are ongoing goalsof the computer industry. Greater integrated circuit density isprimarily limited by the space or “real estate” available for mountingdie on a substrate such as a printed circuit board. Conventional leadframe design inherently limits package density for a given die sizebecause the die-attach paddle of the lead frame must be larger than thedie to which it is bonded. The larger the die, the less space thatremains around the periphery of the die-bonding pad for wire bonding.Furthermore, the wire bonding pads on the standard lead frame provideanchorage for the leads when the leads and the die are encapsulated inplastic. Therefore, as the die size is increased in relation to a givenpackage size, there is a corresponding reduction in the space along thesides of the package for the encapsulating plastic which joins the topand bottom of the plastic body at the mold part line and anchors theleads. Thus, as the leads and encapsulant are subjected to the normalstresses of subsequent forming and assembly operations, theencapsulating plastic may crack, compromising package integrity andsubstantially increasing the probability of premature device failure.

A so-called “leads over chip” (LOC) arrangement eliminates thedie-attach paddle of the lead frame and supports the die by its activesurface from the inner lead ends of the lead frame. This permits a widervariety of bond pad patterns on the die, extends theleads-to-encapsulant bond area and, with appropriate design parameters,can reduce the size of the packaged device for a given die size.

One method of increasing integrated circuit density is to stack dievertically. U.S. Pat. No. 5,012,323 (“the '323 patent”) issued Apr. 30,1991 to Farnworth teaches combining a pair of die mounted on opposingsides of a lead frame. An upper, smaller die is back-bonded to the uppersurface of the leads of the lead frame via a first adhesively coated,insulated film layer. A lower, larger die is face-bonded to the lowerlead frame die-bonding region via a second, adhesively coated,insulative film layer. The wire-bonding pads on both upper die and lowerdie are interconnected with the ends of their associated lead extensionswith gold or aluminum bond wires. The lower die must be slightly largerthan the upper die in order for the die pads to be accessible from abovethrough a bonding window in the lead frame such that gold wireconnections can be made to the lead extensions. This arrangement has amajor disadvantage from a production standpoint, since the differentsize dice require that different equipment produce the different die orthat the same equipment be switched over in different production runs toproduce the different die.

U.S. Pat. No. 5,291,061 issued Mar. 1, 1994 to Ball teaches a multiplestacked die device containing up to four stacked dice supported on adie-attach paddle of a lead frame, the assembly not exceeding the heightof current single die packages, and wherein the bond pads of each dieare wire bonded to lead fingers. The low profile of the device isachieved by close-tolerance stacking which is made possible by alow-loop-profile wire bonding operation and thin adhesive layers betweenthe stacked dice.

U.S. Pat. No. 5,323,060 issued Jun. 21, 1994 to Fogal et al. teaches amultichip module that contains stacked die devices, the terminals orbond pads of which are wire bonded to a substrate or to adjacent diedevices.

U.S. Pat. No. 5,422,435 to Takiar et al. teaches stacked dice havingwire bonds extending to each other and to the leads of a carrier membersuch as a lead frame.

U.S. Pat. No. 5,399,898 issued May 21, 1995 to Rostoker (“Rostoker”)teaches multichip, multitier semiconductor arrangements based on singleand double-sided flip chips. Rostoker discloses bridging a die over andbetween two adjacent dice. However, Rostoker intuitively requires thedie and bond pad bump patterns be specifically designed to achieveproper electrical communication between the bridged die.

Therefore, it would be advantageous to develop a technique and assemblyfor increasing integrated circuit density using non-customized dieconfigurations in combination with commercially available, widelypracticed semiconductor device fabrication techniques.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to an apparatus and a method forincreasing integrated circuit density. The apparatus comprises at leastan upper die and an opposing lower die which is connected to a substrate(the term “substrate” will be used for purposes of this application tomean either substrate carrying traces or other conductors, or aleadframe). The lower die is preferably a flip chip having, for example,C4 solder bump connections, conductive polymer bumps, pin connections,or surface mount J-lead connections extending substantiallyperpendicularly from the face surface of the lower die. The substrate isconfigured with a specific lead end or trace end pattern compatible withthe specific pin out or bump connections on the flip chip.

A layer of adhesive, in some instances an electrically insulativeadhesive as required or desired to electrically isolate adjacent dice,is applied over the back side of the lower die. The back side of theupper die is placed on the adhesive, thereby attaching the upper die tothe lower die, and the adhesive is cured. Preferably, the face or activeside of the upper die includes a plurality of bond pads. Bond wires ofgold, aluminum or other suitable materials as known in the art areattached between the upper die bond pads and a corresponding trace endor lead end on the substrate.

It is, of course, understood that the electrical connection between theupper die and the substrate can be achieved with TAB technology, whereinmetal tape leads are attached between the bond pads on the upper die andthe leads on the substrate. However, such an approach obviously requiresundesirable pre-planning of bond pad and trace end locations forfabrication of the TAB tape.

An encapsulant is generally used to cover the bond wires and metal tapeleads to prevent contamination. Preferably, the exposed circuitry of thedie stack is sealed from contamination by an underflow compound for the(lower) flip chip and a glob top over the entire assembly after wirebonding.

Such an arrangement increases semiconductor device density usingnon-customized die and bond pad patterns, and commercially practicedconductor attachment techniques.

If the upper die is smaller than the lower die, one or more small,additional, discrete components such as resistors, capacitors, or thelike can be attached to the back side of the lower die via a portion ofthe adhesive not covered by the upper die. Bond wires can be attachedbetween the upper die and the discrete component(s), if desired, as wellas between the component(s) and the substrate. This arrangement frees upreal estate on the substrate that would normally be taken up by thecomponent, thereby further increasing potential integrated circuitdensity.

A multitude of die arrangements can be conceived using the technique ofthe present invention. For example, an additional (third) die can beadded to the above arrangement. An adhesive is added to the activesurface or face of the upper die (without covering the bond pads) andthe back side of the additional die is applied to the adhesive, therebyattaching the additional die to the upper die. Preferably, the face sideof the additional die has a plurality of bond pads. Bond wires areattached between the additional die bond pads and corresponding trace orlead ends on the substrate.

Of course, the bond wires can be attached from the additional (third)die to a component attached to the adhesive not covered by the upperdie, and/or, if the additional die is smaller than the upper die, acomponent can be attached to the adhesive on the face of the upper dieand bond wires attached thereto.

As another example, a pair of lower dice can be connected to thesubstrate with the upper die bridged between the lower die. The upperdie is adhered to both lower dice with the layers of adhesive appliedover both lower dice back sides. Bond wires are attached in the mannerdiscussed above. Furthermore, still more additional dice can be stackedor discrete components attached to the assembly in the manner discussedabove.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming that which is regarded as the present invention,the advantages of this invention can be more readily ascertained fromthe following description of the invention when read in conjunction withthe accompanying drawings in which:

FIG. 1 is a side plan view of a preferred assembly of the presentinvention;

FIG. 2 is a side plan view of an alternate assembly of the presentinvention;

FIG. 3 is a side plan view of another alternate assembly of the presentinvention;

FIG. 4 is a side plan view of yet another alternative assembly of thepresent invention; and

FIG. 5 is a side plan view of still another alternative assembly of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates a bare die assembly 10 of the present invention. Theassembly 10 comprises an upper die 12 and an opposing lower die 14 whichis connected to a leadframe or other substrate 16. Fabrication of theassembly 10 comprises providing the lower die 14 having a face surface18 with at least one flip chip electric connection 20 (such as a C4solder bump connection, conductive polymer bump or pin connection, theseand other alternatives being known in the art, by way of example)extending from a bond pad or other terminal 22 on the lower die facesurface 18. The flip chip electric connections 20 extend to a surface 24of the substrate 16 in such a manner that the flip chip electricconnections 20 physically (mechanically) attach to, and make electricalcontact with, lead ends, trace ends, terminals or other electricalcontact elements 26 in or on the surface 24 of the substrate 16. A backside 32 of the upper die 12 is adhered to the lower die 14 with a layerof adhesive 28 applied over a lower die back side 30. An adhesiverequiring a curing step, such as an epoxy, is preferred, although manyadhesives known in the art are suitable.

A face side 34 of the upper die 12 has a plurality of bond pads 36disposed thereon. A plurality of bond wires 38 are attached between theupper die bond pads 36 and corresponding trace or lead ends or otherterminals 40 on the upper surface 24 of the substrate 16.

Preferably, a sealing (underfill) compound 42 as known in the art isdisposed between the lower die 14 and the substrate 16 to preventcontamination of the die-to-substrate board connections 20 and to morefirmly secure the lower die 14 to the substrate 16. A glob top 48 may beapplied over assembly 10 individually as shown in broken lines, or overthe entire substrate 16, which may support a plurality of assemblies 10.The subsequently described embodiments may similarly be glob-topped, asdesired.

Substrate 16, if an insulative substrate, may itself be connected to achassis or mother board by edge connections, bump connections, pinconnections, or other conductive arrangements as known in the art. Ifsubstrate 16 is a lead frame, the outer lead ends may engage ahigher-level package as known in the art.

FIG. 2 illustrates an alternative bare die assembly 50 of the presentinvention. Components common to both FIG. 1 and FIG. 2 retain the samenumeric designation. The assembly 50 comprises a first, lower die 14connected to the supporting substrate or leadframe 16. The lower die 14comprises a face or active surface 18 with at least one flip chipelectric connection 20 extending from the bond pad 22 on the lower dieface surface 18. The flip chip electric connections 20 are made with theupper surface 24 of the substrate 16 in such a manner that the flip chipelectric connections 20 mechanically bond and electrically contact theelectrical contact elements 26 in or on the surface 24 of the substrate16.

A back side 52 of a second die 54 is adhered to the lower die 14 withthe layer of adhesive 28 applied over the lower die back side 30. A faceside 56 of the second die 54 has a plurality of bond pads 58 disposedthereon. A plurality of bond wires 60 is attached between the second diebond pads 58 and corresponding trace or lead ends 40 on the uppersurface 24 of the substrate 16. Additionally, as shown in FIG. 2, if thesecond die 54 is slightly smaller than the lower die 14, an additionalcomponent 62, such as a resistor, capacitor, or the like, may be adheredto the layer of adhesive 28 on the lower die back side 30. Thisarrangement frees up space on the substrate 16 that would normally betaken up by the component 62. A second die-to-component bond wire 64 isattached between a respective second die bond pad 58 and the component62. A component-to-substrate bond wire 66 is attached between thecomponent 62 and trace or lead end 40 on the upper surface 24 of thesubstrate 16.

A back side 68 of a third die 70 is adhered to the second die 54 with asecond layer of adhesive 72 applied on the second die face side 56. Aface side 74 of the third die 70 has a plurality of bond pads 76disposed thereon. A plurality of bond wires 78 is attached between thethird die bond pads 76 and corresponding trace or lead ends 40 on theupper surface 24 of the substrate 16. Wire bonds could also be made fromthird die 70 to component 62, or to yet another discrete componentstacked on and adhered to third die 70.

FIG. 3 illustrates another alternative bare die assembly 80, comprisinga second discrete component 82 adhered to the second layer of adhesive72. A third die-to-component bond wire 84 is attached between arespective third die bond pad 76 and the component 62. A firstcomponent-to-substrate bond wire 66 is attached between the component 62and the upper surface 24 of the substrate 16. A third die-to-secondcomponent bond wire 86 is attached between a respective second die bondpad 76 and the second component 82. A second component-to-substrate bondwire 88 is attached between the component 82 and the upper surface 24 ofthe substrate 16.

It is, of course, understood that a number of configurations of thisembodiment could be constructed, including stacks of more than threedice.

FIG. 4 illustrates a multiple base bare die assembly 90 of the presentinvention. Components common to the previous figures retain the samenumeric designation. The assembly 90 comprises a pair of lower firstdice 14A and 14B connected to the substrate or leadframe 16. The lowerdice 14A and 14B comprise face surfaces 18A and 18B, each having atleast one flip chip electric connection 20A and 20B extendingsubstantially perpendicularly from the bond pads 22A and 22B on thelower die face surfaces 18A and 18B. The flip chip electric connections20A and 20B extend to the upper surface 24 of the substrate 16 in such amanner that the flip chip electric connections 20A and 20B make physicalconnection and electrical contact with the electrical contact elements26 in or on the surface 24 of the substrate 16.

The back side 52 of second die 54 bridges and is adhered to both lowerdice 14 with the layers of adhesive 28A and 28B applied over the lowerdie back sides 30A and 30B. The face side 56 of the second die 54 has aplurality of bond pads 58 disposed thereon. A plurality of bond wires 60is attached between the second die bond pads 58 and corresponding traceor lead ends 40 on the upper surface 24 of the substrate 16. Additionalcomponents 62A and 62B, such as resistors, capacitors, or the like, maybe adhered to the layers of adhesive 28A and 28B on the lower die backsides 30A and 30B. This arrangement frees up space on the substrate 16that would normally be taken up by the components 62A and 62B. A seconddie-to-component bond wire 92 is attached between a respective first diebond pad 58 and the component 62B. A first component-to-substrate bondwire 94 is attached between the component 62B and the upper surface 24of the substrate 16.

The back side 68 of the third die 70 is adhered to the second die 54with the second layer of adhesive 72 applied on the second die face side56. The face side 74 of the third die 70 has a plurality of bond pads 76disposed thereon. A plurality of bond wires 78 is attached between thethird die bond pads 76 and corresponding trace or lead ends 40 on theupper surface 24 of the substrate 16. A third die-to-component bond wire96 is attached between a respective third die bond pad 76 and thecomponent 62A. A second component-to-substrate bond wire 98 is attachedbetween the component 62A to the upper surface 24 of the substrate 16.

FIG. 5 illustrates a second multiple base bare die assembly 100 of thepresent invention. Components common to the previous figures retain thesame numeric designation. The assembly 100 comprises a pair of lowerfirst dice 14A and 14B connected to the substrate or leadframe 16. Thelower dice 14A and 14B comprise face surfaces 18A and 18B, each havingat least one flip chip electric connection 20A and 20B extendingsubstantially perpendicularly from the bond pads 22A and 22B on thelower die face surfaces 18A and 18B. The flip chip electric connections20A and 20B extend to the upper surface 24 of the substrate 16 in such amanner that the flip chip electric connections 20A and 20B make physicalconnection and electrical contact with the electrical contact elements26 in or on the surface 24 of the substrate 16.

The back side 52 of second die 54 bridges and is adhered to both lowerdice 14A and 14B with the layers of adhesive 28A and 28B applied overthe lower die back sides 30A and 30B. The face side 56 of the second die54 has a plurality of bond pads 58 disposed thereon. A plurality of bondwires 60 is attached between the second die bond pads 58 andcorresponding trace or lead ends 40 on the upper surface 24 of thesubstrate 16. An additional component 62, such as a resistor, capacitor,or the like, may be adhered to substrate or leadframe 16 by a layer ofadhesive 65. A second die-to-component bond wire 92 is attached betweena respective first die bond pad 58 and the component 62. Acomponent-to-substrate bond wire 94 is attached between the component 62and the upper surface 24 of the substrate 16.

It is, of course, understood that a number of configurations of thisembodiment could be constructed. For example, multiple bridge dice maybe employed over multiple lower dice; more than three levels of dicecould be stacked; rectangular dice may be stacked with their major axesmutually perpendicular; a conductive die attach adhesive may be employedbetween a flipped base die and an upper stack die so that both dice maybe grounded through the upper die's wire bonds to the substrate; bondpad layouts may be varied, and the like.

Having thus described in detail preferred embodiments of the presentinvention, it is to be understood that the invention defined by theappended claims is not to be limited by particular details set forth inthe above description, as many apparent variations thereof are possiblewithout departing from the spirit or scope thereof.

1. A method of fabricating a multi-die assembly, comprising: providing asubstrate including conductors; securing an active face-down base die tothe substrate electrically connecting the base die with a conductor ofthe substrate; securing an active face-up stack die to the base die;electrically connecting the stack die with a conductor of the substrate;securing another stack die to the assembly; electrically connecting theother stack die wit a conductor of the substrate; securing a discretecomponent to at least one of the stack die, the other stack die, and thebase die; and electrically connecting the discrete component to at leastone of the stack die, the other stack die, and the base die.
 2. Themethod of claim 1, further comprising electrically connecting thediscrete component to a conductor of the substrate.
 3. The method ofclaim 2, further comprising electrically connecting the discretecomponent to at least one other of the stack die, the other stack die,and the base die.
 4. The method of claim 1, wherein electricallyconnecting the discrete component to at least one of the stack die, theother stack die, and the base die includes extending a bond wire betweenthe discrete component and at least one of the stack die, the otherstack die, and the base die.
 5. The method of claim 1, furthercomprising: securing another discrete component to at least one of thestack die, the other stack die, the base die, and the substrate;electrically connecting the other discrete component to at least one ofthe stack die, the other stack die, the base die, and a conductor of thesubstrate; and electrically connecting the other discrete component toat least another of the stack die, the other stack die, the base die,and a conductor of the substrate.
 6. The method of claim 1, whereinsecuring the stack die to the base die further includes providing alayer of epoxy adhesive between the stack die and the base die.
 7. Themethod of claim 6, wherein providing a layer of epoxy adhesive includesproviding a layer of electrically conductive epoxy adhesive.
 8. Themethod of claim 7, further comprising electrically grounding the basedie and the stack die via the layer of electrically conductive epoxyadhesive.
 9. The method of claim 6, wherein securing a layer of epoxyadhesive between the stack die and the base die further includes curingthe layer of epoxy adhesive.
 10. The method of claim 1, wherein securingthe other stack die to the assembly includes securing the other stackdie to the stack die.
 11. The method of claim 1, further comprisingattaching a second active face-down base die to the substrate andelectrically connecting the second base die with a conductor of thesubstrate.
 12. The method of claim 11, further comprising bridging thestack die between the base die and the second base die.
 13. The methodof claim 12, further comprising: securing an other discrete component toat least one of the stack die, the base die, the second base die, andthe substrate; and electrically connecting the other discrete componentto at least one of the stack die, the base die, the second base die, anda conductor of the substrate.
 14. The method of claim 13, furthercomprising electrically connecting the other discrete component to adifferent at least one of the stack die, the base die, the second basedie, and a conductor of the substrate.
 15. The method of claim 12,further comprising attaching an additional stack die to the bridge stackdie.
 16. A method of fabricating a semiconductor device, comprising:attaching analogous sides of a first die and second die; securing adiscrete component to at least one of the first die and the second die;and electrically connecting the discrete component to at least one ofthe first die and the second die.
 17. The method of claim 16, whereinattaching analogous sides of the first die and the second die includesattaching the first die and the second die back-to-back.
 18. The methodof claim 16, further comprising attaching the first die to a substrateincluding conductors.
 19. The method of claim 18, wherein attaching thefirst die to the substrate includes attaching an active face of thefirst die to the substrate.
 20. The method of claim 18, furthercomprising electrically connecting the first die to a conductor of thesubstrate.
 21. The method of claim 20, wherein electrically connectingthe first die to a conductor of the substrate includes at least one ofrefluxing a solder ball, curing a conductive polymer ball, soldering apin, and soldering a J-lead.
 22. The method of claim 18, furthercomprising electrically connecting the discrete component to a conductorof the substrate.
 23. The method of claim 18, further comprisingelectrically connecting the second die to a conductor of the substrate.24. The method of claim 16, further comprising electrically connectingthe discrete component to both the first die and the second die.
 25. Themethod of claim 16, wherein attaching analogous sides of the first dieand the second die includes attaching analogous sides of the first dieand the second die such that the first die is laterally offset relativeto the second die.
 26. The method of claim 25, further comprisingattaching an analogous side of a third die to the second die.
 27. Themethod of claim 26, further comprising attaching another discretecomponent to at least one of the first die, the second die, and thethird die and electrically connecting the other discrete component to atleast one of the first die, the second die, and the third die.
 28. Themethod of claim 27, further comprising electrically connecting the otherdiscrete component to at least another of the first die, the second die,and the third die not previously electrically connected to the otherdiscrete component.
 29. The method of claim 16, further comprisingattaching an additional die to the second die.
 30. A method ofassembling dice, comprising: mounting a plurality of dice over asubstrate, wherein at least two dice of the plurality exhibit differentelectrical connections to conductors of the substrate; and mounting adiscrete component to one of the plurality of dice, wherein the discretecomponent is electrically connected to at least one of the plurality ofdice.
 31. The method of claim 30, further comprising extending a wirebond to electrically connect one die of the at least two dice with aconductor of the substrate.
 32. The method of claim 30, wherein mountingthe die over the substrate includes forming a flip-chip arrangement withat least one of the at least two dice.
 33. A method of fabricating asemiconductor device, comprising: mounting a plurality of dice over asurface of a support structure, wherein at least one die's contact padsface towards the support surface and at least one other die's pads faceaway from the support surface; and mounting a discrete component on atleast one of the plurality of dice.
 34. The method of claim 33, furthercomprising electrically connecting the plurality of dice to at least oneconductor of the support surface.
 35. The method of claim 33, furthercomprising electrically connecting the discrete component to at leastone die of the plurality of dice.
 36. The method of claim 35, furthercomprising electrically connecting the discrete component to a conductorof the support surface.
 37. A method of fabricating a multi-dieassembly, comprising: providing a substrate including conductors;attaching at least one base die to the substrate in electricalcommunication with a conductor of the substrate; attaching at least oneother base die to the substrate in electrical communication with aconductor of the substrate; attaching at least one stack dieback-to-back with the at least one base die and the at least one otherbase die such that the at least one stack die bridges the at least onebase die and the at least one other base die; electrically connectingthe at least one stack die to a conductor of the substrate; securing atleast one discrete component to at least one of the at least one stackdie, the at least one base die, the at least one other base die, and thesubstrate; and electrically connecting the at least one discretecomponent and at least one of the at least one stack die, the at leastone base die, the at least one other base die, and a conductor of thesubstrate.
 38. A method of fabricating a dice stack, comprising:providing a substrate including conductors; attaching two base dice tothe substrate, each being in electrical communication with at least oneconductor of the substrate; bridging the two base dice with a stack diesuch that similar sides of the stack die and the two base dice areattached; electrically connecting the stack die to a conductor of thesubstrate; securing a discrete component to at least one of the stackdie, at least one of two base dice, and the substrate; and electricallyconnecting the discrete component and at least one of the stack die, atleast one of the two base dice, and a conductor of the substrate. 39.The method of claim 38, wherein attaching two base dice to the substratefurther includes attaching an active face of at least one of the twobase dice to the substrate.
 40. A method of fabricating a multi-dieassembly, comprising: providing a substrate including conductors;securing a base die to the substrate electrically connecting the basedie with a conductor of the substrate; securing a stack die to the baseddie with a layer of electrically conductive epoxy adhesive; providing adirect electrical path between the stack die and a conductor of thesubstrate; and electrically grounding the at least one base die via thelayer of electrically conductive epoxy adhesive and the at least onestack die.